Thin-film thermoelectric devices for on-chip cooling and energy harvesting
Abstract
Recent advances in nano-structured thermoelectric (TE) materials have renewed the interest in on-chip applications of TE materials like energy harvesting and hot-spot cooling. This research aims to investigate the feasibility of thin-film TE materials for on-chip applications through device, circuit, and architecture simulations. First, we evaluate the optimal geometry and placement of thin-film TE modules (TEM) within a chip package using a finite element model that captures the three-dimensional nature of heat-flow in the package. We also show that the end-to-end efficiency of the on-chip energy harvester can be optimized by co-designing the TEM's geometry with the circuit elements of an inductive power converter (PC). The impact of TEM's contact parasitics on the conversion efficiency of the PC circuit is also quantified. Second, we analyze the relative importance of TE parameters and contact parasitics on the cooling performance using the mathematical framework of sensitivity analysis. The results indicate that the components of power-factor ( S and σ) have a higher influence than the thermal conductivity (κ) on the performance of a TE cooler. In presence of significant contact parasitics, we find that the carrier concentration resulting in best cooling and harvesting is lower than that of highest ZT. Finally, to evaluate the workload dependent performance of on-chip TE devices, we developed a hierarchical simulation methodology that connects an architectural simulator and a power estimation tool with a thermal simulator capable of simulating TE devices. Using this framework, we evaluate the cooling and energy harvesting potential of on-chip TE devices across the SPEC2000 workloads.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Computer Engineering|Electrical engineering
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