Physics and simulation study of nanoscale electronic devices

Saumitra R Mehrotra, Purdue University

Abstract

Silicon based CMOS technology has seen continuous scaling of device dimensions for past three decades. There is a lot of focus on incorporating different high mobility channel materials and new device architectures for post-Si CMOS logic technology, making it a multifaceted problem. In this thesis some of the multiple challenges concerning new CMOS technologies are addressed. High carrier mobility alloyed channel materials like SiGe and InGaAs suffer from scattering due to disorder called, alloy scattering. The current theory of alloy scattering present in literature/text books can be called rudimentary at the best due to lack of a strong theoretical foundation and/or use of fitting parameters to explain experimental measurements. We present a new atomistic approach based on tight-binding parameters to understanding the alloy disorder. Using this approach we are able to provide new insights into the theory of alloy scattering and explain the experimental measurements in bulk SiGe and InGaAs that were till now based on just fitting parameters. With an updated understanding of alloy scattering, hole mobility in SiGe nanowires is calculated using a linearized Boltzmann formalism. Bulk Ge exhibits high hole mobility makeing it ideal for PMOS devices. Nano patterning of Ge/SiGe leads to Ge nanofins with both uniaxial and biaxial strain components, making it a device architecture design problem. Fully atomistic simulations involving molecular dynamics (ReaxFF force field) based relaxation for strain relaxation; tight-binding based bandstructure calculations and a linearized Boltzmann transport model for mobility calculations are performed. Final phonon mobility calculations reveal nearly 3.5 X improvements compared to biaxial strained Ge in Ge nanofins with width reduction. High electron mobility III--V's are projected to be a material of choice for post-Si NMOS. These low electron mass materials suffer from the 'DOS bottleneck' issue. Transistor designs based on using mixed Gamma-L valleys for electron transport are proposed to overcome the density of states (DOS) bottleneck. Improved current density over Si is demonstrated in GaAs/AlAsSb, GaSb/AlAsSb, and Ge-on-Insulator-based single gate thin-body n-channel transistors. Finally, a critical question that has to do with scaling is - How small a useful MOS transistor can be? As transistor channel lengths are scaled to lengths shorter than Lg < 8 nm, direct source-drain tunneling starts to limit the transistor operation. Scaling approaches needed in this tunneling dominated regime are discussed using atomistic quantum mechanical simulations.

Degree

Ph.D.

Advisors

KLIMECK, Purdue University.

Subject Area

Electrical engineering|Nanoscience

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