Variation-derived chip security and accelerated simulation of variations

William Paul Griffin, Purdue University

Abstract

In modern ICs, variations can be quite troublesome. Ensuring quality and yield requires careful and resource-intensive simulation under the effects of parameter variations. Threshold voltage approximation of parameter variations can help accelerate simulations, but it comes with unknown losses in quality. Instead, we propose a parameter reduction technique designed to minimize quality loss through careful analysis of the source transistor model and the set of input parameter variations. Using Pao-Sah's Double Integral model, we demonstrate the relative quality of our reduced parameter approach versus threshold voltage approximation. Despite their negative role in circuitry, variations can be useful for security applications. They can be used both to provide a fingerprint for any chip, as well as to generate truly random numbers. Using these properties, we have developed two security-related chip enhancements: a chip antipiracy scheme, and a secure nonvolatile cache. To prevent chip cloning, we require a unique key to operate every manufactured chip by leveraging the nonreplicable nature of variations. Through minor modifications, we create a system in which process variation sensors can be integrated into any logic block so that the block itself authenticates the key. Finally, the anticipated use of leakage-free nonvolatile caches presents a disruption to the processing security assumption that memory values are not retained upon power loss or system reset. To prevent against data leakage, we propose the use of truly random, single boot keys, along with a multistage encryption mechanism. We offer insurance against the possibility of a cryptographic break by implementing a two-level encryption scheme that offers cache-level data confidentiality with minimal impact on system performance.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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