Characterization and modeling of variability and reliability in CMOS/poly-Si technology
Abstract
The continuous demand for higher performance and lower power consumption has driven aggressive scaling of technology. However, due to increasing variability in scaled technologies, supply voltage reduction is limited by the guard-band which is roughly determined by the worst case conditions. The variability in devices arises from both inherent variations (process variations or grain boundary (GB) in the poly-Si technology) and randomness of the reliability phenomena (bias temperature instability (BTI), time-dependent dielectric breakdown (TDDB), hot carrier injection (HCI), etc). This research focuses on device design, characterization and modeling of variability and reliability in CMOS/poly-Si technologies. First, we explore variability due to grain boundary (GB) in low-temperature poly-Si thin film transistor (LTPS TFT) technology. We present a device design/optimization methodology with scaling of buried-oxide (BOX) thickness, resulting in suppressing BOX-induced barrier lowering (BIBL) for improving gate-controllability and reducing VT-variability. We also report that owing to negligible substrate-loss, passive devices in LTPS TFT technology have high quality factor, capable of compensating poor device characteristics for better radio frequency (RF) operation. Next, we propose a physics-based SPICE model to estimate the increase in the gate leakage current due to TDDB and the breakdown statistics in ultra thin-oxides. By incorporating the TDDB model in simulation tools like SPICE, circuit performance due to TDDB-induced degradation can be predicted at the circuit level of design abstraction. We also explore TDDB impacts on the frequency response of ring oscillator and cell stability and performance in memory circuits using the proposed model.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our
proxy server.