Non-planar 3D iii-v mosfets for high-speed low-power logic applications
Abstract
Recently, significant progress has been made in the understanding and improvement of high-k/III-V semiconductor interfaces. However, to realize III-V MOSFETs beyond the 14nm technology node, emerging 3D device structures are necessary to suppress short-channel effects. In this thesis, fabrication and characterization of advanced non-planar 3D III-V MOSFETs are demonstrated and summarized, including buried-channel InGaAs FinFETs, InGaAs-on-nothing nanowire MOSFETs, InGaAs gate-all-around nanowire MOSFETs. A novel InGaAs nanowire release process and an atomic-layer deposited high- k/metal gate process has been developed to enable the fabrication process of the InGaAs gate-all-around FET with channel length down to 20nm. Near-ideal subthreshold swing of 63mV/dec and drain induced barrier lowering of 7mV/V has been demonstrated, thanks to the excellent electrostatic control of the gate-all-around structure. Vertically stacked InGaAs nanowire MOSFETs has also been fabricated for the first time, leading to 4 × increase in drive current. Non-planar 3D III-V MOSFETs are very promising candidate for future high-speed low-power logic applications.
Degree
Ph.D.
Advisors
Ye, Purdue University.
Subject Area
Electrical engineering
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