Technology-circuit co-design and analysis of nano-scale multi-gate fets for memory applications
Abstract
Multi-gate FETs are emerging as promising devices for scaled technologies due to their superior gate control of the channel compared to conventional MOSFETs. In order to utilize the full potential of multi-gate FETs, there is a need for design methodologies which exploit unique technology features to achieve superior design solutions. Moreover, design issues specific to multi-gate FETs need to be identified and addressed using innovative techniques at different levels of design abstraction. This research focuses on device/circuit-level design and analysis of multi-gate FET based SRAMs. For our analysis, we have developed a mixed-mode simulation framework, with the capability of treating quantum mechanical effects in deeply scaled devices. The simulation framework is based on non-equilibrium Green's function (NEGF) models and Taurus simulations for devices. Circuit simulations are carried out using HSPICE with look-up table based Verilog-A models. Using this simulation framework, we explore the device-circuit interactions in multi-gate FET based SRAMs. First, we show that using unique technology features of FinFETs (a type of multi-gate FET), design conflicts in 6T SRAM can be mitigated. To that effect, we propose FinFETs with asymmetric gate underlap and asymmetric source/drain doping to mitigate the read-write conflict in SRAMs and achieve larger cell stability along with leakage reduction. We also explore independent gate FinFET based SRAMs and propose design techniques to improve the cell stability. Next, we propose a double-gate heterojunction intra-band tunnel (HIBT) FET based on different source/drain and channel materials. We show that compared to Si double-gate MOSFET, HIBT FET exhibits lower drain-induced barrier lowering/thinning and lower sensitivity of OFF current to process variations. We also discuss the suitability of the proposed device for low voltage SRAMs. Finally, based on some unique features of FinFETs, we report the possibility of negative-bias temperature instability in n-type silicon-on-insulator FinFETs used as access transistors in SRAMs and analyze its impact on the cell stability and performance.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering|Nanotechnology
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