Design and optimization of low power PLL frequency synthesizer

Wu-Hsin Chen, Purdue University

Abstract

The development of wireless sensor networks and low-power SoC applications high-lights the importance of ultra-low-voltage, ultra-low-power designs. While reducing voltage is one of the most efficient ways to decrease power consumption, low voltage designs usually suffer from small design margins and high sensitivity of process-voltage-temperature variations, imposing a huge design challenge on digital, analog and mixed-signal circuit designs, and phase-locked loop (PLL) is one of the examples. As a widely used clock generator in mixed-signal designs, the implementation of ultra-low voltage PLL in deep-submicron technologies becomes the bottleneck for successful low-power system integration. In this dissertation, the challenges of ultra-low-voltage designs in the PLL are discussed extensively. In order to address low-voltage design challenges, analog design techniques and self-calibration architectures applying to individual blocks and the architecture of PLL are proposed in this dissertation, including cross-coupled charge pump, dual resistor-varactor tuning voltage-controlled oscillator, implication-logic-based prescaler, and power calibration techniques. An ultra low-power PLL using proposed techniques is also presented to demonstrate the performance of the proposed techniques. The PLL is specially designed for the magnetic sensor network in ISM band with an output frequency ranging from 400 to 433MHz. Implemented in 130nm CMOS technology, the total power of the PLL is reduced to 440μW with a phase noise performance of −98dBc/Hz at 1MHz frequency offset. The figure-of-merit of the proposed ultra low-power PLL is significantly better than that of the state-of-the-art designs.

Degree

Ph.D.

Advisors

Jung, Purdue University.

Subject Area

Electrical engineering

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