Spintronic memory and logic: From atoms to systems

Charles Augustine, Purdue University

Abstract

As Si-CMOS scaling is predicted to reach fundamental physical limits in the next 10 years, there is an immediate need to explore and develop alternate devices/switches, which will enable us to continue the design of energy efficient, high-performance and scalable systems. Devices based on electron spin have gained prominence in the past decade due to almost zero standby-leakage, making them very suitable for memory implementation. On the other hand, for logic, electron spin based implementations can be promising due to the possibility of having low-voltage switches and enhanced functionality logic gates, leading to significant power savings. The primary focus of this research is to explore scalability, power consumption, and speed, from Atoms to Systems, considering electron spin as the alternate state variable for both logic and memory. In order to do that we have investigated self-consistent atomistic simulation framework for spin based devices based on Non-Equilibrium Green's Function (NEGF) formalism and Four Component Spin Transport model for spin-transport and Landau-Lifshitz-Gilbert (LLG) equation for magnet dynamics. Circuit and architecture level analysis are based on the device performance obtained using the proposed framework. Specifically, we have explored spin-transfer torque (STT) based 1T-1R bit-cell and domain wall memories (DWM) using nanomagnetic strips. For 1T-1R memory, four different bit-cells are systematically studied from embedded memory applications. On the other hand, for DWM, experimentally benchmarked model was used to optimize memory structure for readability, writabiity, stability and scalability through material and geometrical parameters. From logic design perspective, we have explored three types of spin-torque devices, each with distinct advantages and disadvantages. Finally, a non-Boolean logic implementation framework using spin-based logic devices was developed to design circuits optimized for ultra-low power and high performance.

Degree

Ph.D.

Advisors

ROY, Purdue University.

Subject Area

Electrical engineering

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