Algorithms and methodologies for routability-driven VLSI placement

Kalliopi Tsota, Purdue University

Abstract

Very large scale integration (VLSI) has been a central technology for the realization of modern-day systems. The number of components in a VLSI design may run in the billions and it continues to grow, while the advantages associated with these advances are realized in multiple fields. However, the increased complexity of the designs poses new challenges for today's electronic design automation. VLSI computer-aided design tools have to address the effects of technology scaling on interconnects. More specifically, interconnect delay has become a dominant factor in modern designs. During the physical design process, placement of the components on a chip and routing of the connections among them are performed, and the final routed wirelength is used as a metric for determining the performance of the design. By minimizing final routed wirelength, power dissipation and interconnect delay can be reduced. The purpose of this Dissertation is to examine the implications of nanometer-scale VLSI technology in the physical design process and to introduce effective approaches to facilitate the overall physical design flow. With this objective, a clustering algorithm, called SafeNet, is developed in the context of VLSI placement, in order to improve both scalability and performance of the placer. The clustering algorithm applies fine clustering of the hypergraphs, thereby preserving the connectivity of the original VLSI circuits and avoiding any significant modification. Moreover, a flat placement algorithm, called PlaceD, is developed as an approach to the wirelength-driven placement problem on application-specific integrated circuits. The algorithm formulates the placement problem as a non-linear constrained optimization problem and applies size scaling in order to minimize the total wire-length of the design, starting with an initial placement obtained using an optimal region-based approach. Simultaneously, the placement algorithm also satisfies various placement constraints. Furthermore, a two-level placement algorithm, called PlaceR, is proposed to address the routability-driven placement problem. This placement algorithm estimates the routed wirelength during global placement using wire density. After the routed wirelength inside multiple regions is estimated, the algorithm incorporates the routability information into an objective function for the global placement in order to guide the placement process. PlaceR also combines a method for the spreading of wire density with clustering, pin congestion control, and size scaling. In this way, the placer minimizes wire congestion and the final routed wirelength of the design. Finally, a post-processing algorithm for placement, called Allagi, is developed to further improve the placement quality. The algorithm formulates the placement problem as a linear program and reduces the total routed wirelength by identifying congested regions in the design. Circuit components that have been placed in the congested areas of the design are relocated to regions that are optimal in terms of minimizing wirelength. The path for the minimization of congestion and improvement in routability is a necessary step for achieving design optimization and enhancing performance. Empirical results show that the proposed methods efficiently reduce the wirelength and improve the routability of the designs. Each of these methods can be incorporated in the overall physical design flow to improve the placement solution and facilitate the operation of a router.

Degree

Ph.D.

Advisors

Balakrishnan, Purdue University.

Subject Area

Engineering|Electrical engineering|Computer science

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