Design guidelines for high efficiency photovoltaics and low power transistors using quantum transport

Samarth Agarwal, Purdue University

Abstract

Energy consumption has become an issue that needs to be addressed on various fronts. Semiconductor technology plays a vital role in different areas where the matter needs attention. In the field of photovoltaics the use of a high band-gap material capable of targeting the high energy photons in the so called “green gap” of the solar spectrum could take the efficiency of multi-junction solar cells beyond 50%. Though InGaN shows some potential, it suffers from phase separation of InN and a high defect density. A material system capable of targeting the “green gap” and alleviating the difficulties in fabrication is required. Equally important is the issue of power consumption in transistors. The supply voltage scaling of transistors which has a direct bearing on the power consumption, has not followed the dimensional scaling of transistors. This is mainly because MOSFETs are fundamentally limited to a 60mV/dec subthreshold slope. Alternate channel materials or new devices are required to allow for a more aggressive supply voltage scaling. In this work, using an atomistic full-band quantum description of nanoscale devices, design guidelines that seek to address each of these issues are suggested. For multi-junction solar cells the ZnSe/GaAs system has been proposed as a viable alternative. Using atomistic tight-binding the band-gap of the ZnSe/GaAs (001) superlattice as a function of the constituent monolayers is investigated. The possibility of engineering a range of bandgaps with the same material system, with a view to achieving the optimum value for solar cells and light emitting diodes, is proposed. For the purpose of supply voltage scaling, Tunnel Field Effect Transistors (TFETs) are promising devices because there is no lower limit to the subthreshold slope. Traditional TFET geometries suffer from low ON currents. Using an atomistic full-band quantum transport solver, a vertical TFET geometry that offers larger tunneling area and hence larger ON currents is investigated. The benefits of a global tunneling model for band to band tunneling over other approaches is highlighted. Finally, a design modification that reduces the lateral leakage current in the vertical TFET geometry making it suitable for low power logic applications, is proposed.

Degree

Ph.D.

Advisors

Reifenberger, Purdue University.

Subject Area

Electrical engineering|Condensed matter physics

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