Low-power, process and error tolerant circuit design for nanometer technologies

Ashish Goel, Purdue University

Abstract

As the CMOS technology continues to scale down, robustness of the circuit with respect to process variations and soft error are becoming major obstacles for circuit design in the nano-scale regime. In this work, we have focused on storage elements – to improve the yield loss in SRAMs due to process variations and to design soft error tolerant flip-flops. Storage elements are particularly important for maintaining the correct state of the system. Among them, SRAMs are particularly vulnerable to failures due to process variations resulting in reduced yield. The main problem with SRAM design is the conflicting requirements for read stability and writeability. We first develop an architecture-aware bit-cell design technique that addresses this underlying issue in SRAM design. We skew the SRAM bit-cell design towards improving read stability and/or access time at the expense of writeability (write failures might increase). We handle the increased write failures at the architectural level by allowing write operations to take an additional cycle to complete. This allows us to improve the yield and lower the operating VMIN significantly without any area overhead. In the second part of the thesis, we propose a general circuit-aware device optimization methodology for sub-50nm FinFET devices and use it for SRAM design. We propose to optimize asymmetric drain spacer extension in FinFETs to achieve simultaneous improvement in read stability and writeability at the cost of access time and area in a 6-T SRAM array. Finally, we propose a class of low-overhead flip-flops suitable for soft error detection/correction. The design reuses Design-for-Test (DFT) logic elements to reduce the area and power overhead compared to the existing designs.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Computer Engineering|Electrical engineering|Nanotechnology

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