Scaling of indium gallium arsenide MOSFET into deep submicron regime

Yanqing Wu, Purdue University

Abstract

As the Si CMOS roadmap for scaling approaches its fundamental physics limits, alternatives have been extensively pursued for the future generation switches. III-V compound semiconductors, especially In-rich InGaAs, have attracted many efforts mainly because of its electron high mobility and velocity. Planar MOSFETs with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/μm has been achieved at Vds = 2.0 V with 5 nm Al2O3 as gate dielectric. gm can be further improved to 1.3 mS/μm by reducing the gate oxide thickness to 2.5 nm at Vds = 1.6 V. HBr pre-treatment, retro-grade structure and halo-implantation processes are introduced for the first time into III-V MOSFET to further improve high-k/InGaAs interface quality and on-state/off-state performance of the devices. The key transistor scaling metrics such as subthreshold slope (S.S.), drain-induced barrier lowering (DIBL), threshold voltage (VT) of these treated devices are compared with channel lengths from 250 nm to 150 nm. To improve the short-channel effect (SCE) which severely affects the transistor output performance, the first well-behaved inversion-mode InGaAs FinFET with ALD Al2O3 as gate dielectric has been demonstrated. Using a damage-free sidewall etching method, FinFETs with Lch down to 100 nm and WFin down to 40 nm are fabricated and characterized. Compared with the planar InGaAs MOSFETs at similar gate lengths, FinFETs have much better electro-static control and show improved output characteristics and less degradation at elevated temperatures. The SCE of III-V MOSFETs is greatly improved by the 3D structure.

Degree

Ph.D.

Advisors

Ye, Purdue University.

Subject Area

Electrical engineering

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