Low voltage robust memory circuit design
Abstract
Aggressive scaling of transistor dimensions with each technology generation has resulted in increased integration density and improved device performance at the expense of increased leakage current. Supply voltage scaling is an effective way of reducing dynamic as well as leakage power consumption. However the sensitivity of the circuit parameters increases with reduction of the supply voltage. SRAM bitcells utilizing minimum sized transistors are susceptible to various random process variations. Hence reducing the memory operating supply voltage (Vmin), while maintaining the yield is becoming extremely challenging in nano-scale technologies. This research focuses on developing novel circuit techniques for robust memory operation with lower Vmin. Three novel process variation tolerant SRAM bitcells are proposed. Measurement results on three test-chips fabricated using 130nm and 90nm technologies confirmed the effectiveness of proposed SRAM bitcells in lowering the Vmin. In addition, low power circuit design techniques for non-silicon technologies such as Magnetic Random Access Memories (MRAM) and compound semiconductor devices are also explored.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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