Voltage-scalable adaptive system design for low power and error resilience in nanometer technologies

Swaroop Ghosh, Purdue University

Abstract

As CMOS approaches the end of the technology roadmap, several new challenges are emerging in the design of integrated circuits (ICs). CMOS devices have been scaled down aggressively in the last few decades to achieve integration density and exponential growth in computing power. As the feature size of transistors get smaller, fabricating processes become increasingly complex. Several corrective design-for-manufacturing steps are employed to avoid hard defects such as shorts/opens/bridges during manufacturing. However, it is not possible to completely eliminate the possibility of these defects. On the other hand, increased die-to-die and within-die parameter variations (e.g., variation in channel length, oxide thickness, number of dopants etc.) have caused parametric failures in logic and memories leading to further loss in yield. Therefore, failures are inevitable in scaled technologies but the traditional approaches to address these issues may not work. For example, (a) Gate upsizing or upscaling of supply voltage to mitigate the process variations increase the power consumption which has detrimental effects on system reliability (due to hot-spots, NBTI, oxide breakdown etc). On the other hand, the standard low power techniques like dual-threshold design or multi-supply islands increase the number of critical paths; degrading the robustness. (b) Triple modular redundancy and mapping-out of failing parts to tolerate the manufacturing defects increase the die-area/power and may not work under higher defect densities. Therefore, the standard approaches to deal with power, process variation and defects are ineffective in future process generations. This dissertation addresses the issues related to low power and errors (both process and manufacturing related) in a collective fashion. We have introduced the concept of critical path isolation and adaptive clock stretching to design voltage scalable and error resilient systems. In particular, we have shown the feasibility of this approach at both the circuits as well as micro-architecture level of abstraction. The first part of this thesis describes CRISTA, a novel paradigm for low-power, variation and temperature tolerant circuits and system design, which allows aggressive voltage over-scaling. The CRISTA design principle (a) isolates and predicts the paths that may become critical under process variations, (b) ensures that they are activated rarely, and (c) avoids possible delay failures in the critical paths by adaptively stretching the clock period to two-cycles. This allows us to operate the circuit at reduced supply voltage while achieving the required yield with small throughput penalty (due to rare two-cycle operations). We have presented three applications of CRISTA methodology, (a) voltage scalable execution unit design; (b) low voltage pipeline design; and, (c) temperature-adaptive circuit/system design. As a proof-of-concept, we designed a two-stage pipelined ALU in IBM 130nm technology. We have also demonstrated the feasibility of CRISTA at micro-architectural level for adaptive temperature management. In the second part of the thesis, we explored the concept of adaptive clock stretching for self-repair in presence of hard faults. We developed a low overhead adaptive technique at circuits and micro-architecture level to perform correct computation in the presence of failures. This is achieved by selective replication and adaptive clock stretching (with negligible IPC degradation) to exploit the spatial and temporal redundancy present in high speed execution units. Finally, we proposed a self-calibration technique for adaptively tuning the source bias of memories under process variation. This allows us to reduce the leakage power aggressively while being resilient towards the retention failures.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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