Self-Aligned Wafer-Level Integration Technology (SAWLIT) with high density interconnects for RF and optoelectronics application
Abstract
The trend for future microelectronics is towards low cost, high performance and multi-functional integrated systems. This research presents a solution to substantially reduce the cost of integrated systems while enhancing their performance. This is achieved through the introduction of a Self-Aligned Wafer Level Integration Technology (SAWLIT) that is suitable for integrating mixed signal, RF, optoelectronic and MEMS circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die to die interconnects are achieved. To demonstrate the capabilities of this integration technology, two system implementations are shown. First, a 10GHz RF receiver designed in 0.18μm CMOS technology is integrated with a high-ρ Silicon substrate and other embedded components. By adjusting the input matching of the 10GHz receiver through the addition of embedded passives, the performance of the front-end module has been improved. The second implementation is a 10Gb/sec optoelectronic receiver that is designed and heterogeneously integrated using a CMOS transimpedance (TIA) amplifier and an InGaAs/InP PIN photodiode for near infrared (1.3 to 1.55μm) applications. The proposed integration technology has been modified to demonstrate a new mixed-signal substrate crosstalk suppression technique. Through sidewall metallization of cavities surrounding individual dies, a truly grounded faraday-cage structure has been realized. Experimental characterizations prove that substantial crosstalk suppression in the order of measurement noise floor can be achieved. Finally, electrical characterization and reliability of Parylene-N as a flexible substrate, multi-layer dielectric material and passivation layer for microwave and millimeter-wave integrated circuits are presented. As a flexible substrate, Parylene-N measures a very low dielectric constant and an extremely low dielectric loss (tanδ < 0.0006) for frequencies up to 60GHz. As a passivation layer, Parylene-N causes insignificant modifications to the properties of underlying passive and active structures. Combination of the proposed self-aligned wafer-level integration technology with low dielectric constant low loss multi-layer Parylene-N facilitates the development of future 3-Dimensional microwave integrated systems. The combined technology provides ultimate flexibility and multi-functionality through integration of heterogeneous chips, high quality factor passive components and non-planar structures such as packaged RF MEMS devices.
Degree
Ph.D.
Advisors
Mohammadi, Purdue University.
Subject Area
Electrical engineering
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