Ultralow power and process variation tolerant VLSI circuit design in nano-scale technologies

Myeong-Eun Hwang, Purdue University

Abstract

Efficient power management is becoming increasingly important with the rapid growth of portable, wireless, and battery-operated applications. Lowering the supply voltage reduces the dynamic power quadratically and leakage power exponentially. Hence, supply voltage scaling has drawn major attention for the low power design. This has resulted in circuits operating at a supply voltage lower than the threshold voltage of a transistor [1]. However, the remarkable decrease in power consumption at ultralow voltage operation is achievable at the cost of processor performance and circuit robustness under process and temperature variation. As the supply voltage is lowered the sensitivity of the circuit electrical parameters to process variation increases [2-4]. Further, the circuit with a lowered voltage becomes more vulnerable to the random noise sources, such as thermal noise and soft error, which are not reduced with supply voltage scaling. As a result, the impact of process variation limits the circuit operation at low supply voltages, particularly memories [5,6] as well as logic [8,9]. Further, embedded cache memories are expected to occupy 90% of the total die area of a system-on-a-chip [10,11]. In order to efficiently address these issues we need an integrated circuit-technology-architectural optimization approach to process resilient IC design. This thesis discusses logic and memory design methodologies for ultralow voltage operations with three main chapters: (1) ultralow power VLSI circuit design under process variations; (2) read-error free subthreshold SRAM design for ultralow power applications; (3) gate-interconnect interdependent delay model for different regions of operation.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Environmental engineering

COinS