Modeling and simulation of VLSI interconnects

Jitesh Jain, Purdue University

Abstract

With aggressive technology scaling, the accurate and efficient modeling and simulation of interconnect effects have become problems of central importance. In a three-dimensional interconnect structure there can be significant coupling, both inductive and capacitive, between interconnects. Models that capture these effects tend to involve large matrices, resulting in extraordinary demands on memory; simulation with these models requires prohibitive amounts of computation. In this work, we present efficient techniques for the fast and accurate modeling and simulation of large-scale on-chip interconnects. (1) Modeling. We have developed efficient and accurate techniques for the extraction of parasitic parameters of large-scale interconnect structures. In the first work, we propose new, exact, closed-form expressions for the scalar mutual and self-potential coefficients for rectangular conductors. These formulas are much better-conditioned than the existing expressions, and can be used for accurate capacitance extraction over wider geometries. Inductance extraction has been a fundamental problem in the modeling and analysis of VLSI interconnects. In the second work, we use the so called 'band-matching' technique for fast and accurate extraction of inductance of interconnect wires. The most computationally intensive step in inductance extraction is inversion of the impedance matrix. We exploit the inherent sparsity structure of the inverse of inductance matrix, to provide an accurate and fast inversion technique. (2) Simulation. The key idea is to exploit the inherent properties of the problem, such as (i) the structure of underlying matrices, and (ii) the structure of interconnects. In the first work, we reformulate the standard modified nodal analysis equation that makes transparent the structure and sparsity of the matrices underlying the model. In addition to providing a compact set of modeling equations, this reformulation offers the potential of exploiting the structure and sparsity at the simulation level, using linear-algebraic techniques. Tree structures are the most commonly encountered structures in VLSI interconnects. In the second work, we present a technique for fast and accurate simulation of large-scale trees. The numerical efficiency of this technique is realized through a novel tree-traversal algorithm for solving linear systems involving matrices arising from tree structures.

Degree

Ph.D.

Advisors

Balakrishnan, Purdue University.

Subject Area

Electrical engineering

COinS