Exploiting independent gate technology in Multiple-Gate silicon CMOS circuit design
Abstract
Structural renovation in transistor and circuit architectures has historically alleviated the power problem. Today, to further the frontiers of integrated circuit scaling, the semiconductor industry boldly considers structural renovation in classical material stacks, processes and planar single-gate MOSFET architecture. In this work, options for emerging Multiple-Gate MOSFETs are studied for circuit design. In the first part of the work, independent gate technology option is proposed to design noise-tolerant Schmitt Triggers with reduced transistor count, to achieve high-performance/lowpower datapaths, and to improve sizing granularity for high-performance/low-power circuit synthesis. In the second part, zero body effect and high RS/D disadvantages of connected-gate topology in FinFET architecture is addressed. Independent gate technology is demonstrated in conventional Static Random Access Memories (SRAM) to build low leakage large cache arrays, and in varactor design to improve quality factor and tuning range. Though, independent gate technology increases the cost of fabrication by adding extra process step(s)/mask(s), it is expected to be a key enabler to further miniaturization.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our
proxy server.