Low power and robust memory design: Device, circuit and micro-architecture perspectives

Qikai Chen, Purdue University

Abstract

As the CMOS technology continues to scale down to achieve higher performance, considerable power dissipation and reduced reliability in circuit functionality are emerging as major obstacles for circuit designs in the nanometer regime. In current micro-processor design, memory is an essential component. In this research, we have investigated techniques to reduce power consumption and to ensure robustness of memory circuits, in particular SRAM caches, from device, circuit and micro-architecture perspectives. From the device optimization perspective, a circuit-aware device design methodology is proposed for SRAM design. The proposed methodology has achieved significant reduction in SRAM cell leakage and access time, 11% and 7%, respectively, for a conventional 6T-SRAM. Also, we have modeled the impact of asymmetric device underlap on transistor characteristics. The benefits of using asymmetric underlap transistors in SRAM designs are evaluated. In addition, since parametric variations have significant impact on the stability of memory cells, the design and test of memories to ensure correct functionality is of considerable interests. In this work, from a circuit perspective, we have proposed a memory testing technique, which reduces the test application time by 29%. Also, we have explored a modeling technique to study the stability of memory cells under parametric variations. To further explore low power techniques in memory design, novel cache micro-architecture is investigated. In this research, an optimized micro-processor architecture based on dynamic loop detection directed cache (DLDDC ) is proposed. The proposed architecture takes advantages of the frequent executions of loops in program codes. Through dynamic loop detection, accurate way-prediction in set-associative data cache is achieved. The studies show that DLDDC can improve power dissipation in a micro-processor core by 12%, compared to a conventional architecture design. Furthermore, the overheads of DLDDC in terms of area and its own power consumption are negligible.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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