Silicon carbide short channel power DMOSFET: An optimized design
Abstract
This thesis concentrates on low voltage (∼1 kV) 4H-SiC power DMOSFET design. The objective of the thesis is to achieve the smallest possible specific onresistance for 1 kV blocking voltage. 4H-SiC is a wide bandgap (Eg = 3.3 eV) semiconductor with high critical electric field, which makes it suitable for high voltage, high power applications. The main problem for the 4H-SiC MOS devices is the low inversion channel mobility, which makes the channel resistance the most dominant component of the total on-resistance. The exceptionally low inversion channel mobility (∼20 cm2/V-s) is attributed to the high interface state densities near the conduction band edge and the surface roughening caused by high temperature implant annealing. As channel resistance is linearly proportional to both channel mobility and channel length, a self-aligned technology was used to reduce the channel length below 0.5 μm. The fabricated device on 6 μm epilayer produced a specific on-resistance of 9.95 mohm-cm2 for an avalanche breakdown voltage of 900 V. The problem with these devices was the high gate oxide field (6 MV/cm), which implied a poor reliability. To overcome this problem as well as to reduce the specific on-resistance further, an exhaustive simulation study was done and an optimized DMOSFET structure was proposed. The new design includes a novel highly doped current spreading layer and a highly-doped JFET region to reduce the total on-resistance, and a JFET length of 1 μm was used to reduce the gate oxide field at the onset of avalanche breakdown. Moreover, an alignment tolerance of 0.5 μm was used to reduce the cell pitch and thereby the specific on-resistance. Electron beam lithography was used to implement these short features. The fabricated device produced a specific on-resistance of 6.95 mohm-cm2 for a blocking voltage of 1050 V. The specific on-resistance of the fabricated devices was slightly higher than the simulated result (4.0 mohm-cm2) due to unexpectedly high contact resistivities.
Degree
Ph.D.
Advisors
Cooper, Purdue University.
Subject Area
Electrical engineering
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