Technology and circuit design in nanoscale single- and multiple-gate silicon CMOS
Abstract
Challenges to continued technology scaling, such as dynamic power, active and standby leakage, noise immunity and process-induced variations, can be tackled at multiple levels of IC design - technology, circuit and micro-architecture. Typically, design teams adopt approaches to tackle each aspect independently. However, given the prominent challenges facing scaling at every level, and the emergence of new technologies with unique characteristics, there is a need for a holistic or integrated technology-circuit-architecture approach to IC design. First, we propose the application of a dynamic forward back bias voltage larger than or equal to supply voltage, to achieve 70-99.5% standby leakage savings in nanoscale bulk and double-gate SOI CMOS technologies. These techniques, called Digital and Overdriven Back Bias respectively, achieve comparable or better active-mode performance and power to Zero Back Bias at room temperature, but suffer from high active leakage at higher temperatures. A Delay-Adaptive Back Bias scheme is proposed to solve the active leakage problem. Second, we study the double-gate FinFET SRAM technology-circuit design space to understand the interplay of device short-channel-effect (SCE), SRAM area, access time, soft error immunity, stability under process variations and leakage. We demonstrate the unique property of these quasi-planar devices that allows exponential leakage savings at constant area and read access time. We evolve approaches to choosing the right combination of device structure, Vt and Vdd to optimize SRAM stability and leakage. Third, we develop compact physical models for band-to-band tunneling and sub-threshold leakage current in double-gate CMOS. We also develop compact statistical models to analyze the impact of gate length and body thickness variations on leakage and threshold voltage distribution.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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