Placement of VLSI circuits

Chen Li, Purdue University

Abstract

Placement plays a fundamental and critical role in the physical design of integrated circuits. The typical objective of placement is to minimize half-perimeter wirelength (HPWL). To address the timing and layout closure problems brought forth by the aggressive scaling of semiconductor technologies, there is a growing trend in dealing with routing resource constraints and performing physical synthesis techniques in the placement step. In this thesis, we develop techniques at various stages of placement to minimize wirelength and improve routability. In the global placement stage, we consider analytical placement approaches to minimize HPWL. We smooth the HPWL function by recursive extension of two-variable max functions. In the detailed placement stage, we propose a congestion-driven white space allocation approach and an effective local minimization technique to achieve better routability and routed wirelength. We also extend our white space allocation approach as an incremental placement technique to accommodate incremental changes in a placement due to physical synthesis techniques, including gate sizing and buffer insertion.

Degree

Ph.D.

Advisors

Koh, Purdue University.

Subject Area

Electrical engineering

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