Low -power and layout -aware data-path synthesis for nanometer technology

Dongku Kang, Purdue University

Abstract

As VLSI technology advances into the nano regime, several problems are emerging as new design challenges: power dissipation, place-&-route and power supply noise are especially becoming critical issues due to higher levels of integration in smaller area. In this research, we present several design schemes for data-path synthesis that consider the new design challenges. First, we study voltage-partitioned multiple-Vdd design schemes for low-power. By considering voltage partitioning when performing scheduling and allocation using multiple-Vdd, the proposed techniques partition the operations in data paths in terms of their supply voltages, thereby helping in clustering the layout in terms of the supply voltages. Second, we present an interconnect-aware complexity reduction technique for digital filters that minimizes the required amount of computation. The proposed graph theoretic method reduces interconnect delay in critical path and improves performance. Finally, a power supply noise-aware design scheme is presented. By evaluating power supply noise in the early design stage, the proposed methodology generates schedule, allocation and floorplan with improved reliability.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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