Robust and highly efficient datapath design in scaled CMOS technologies

Woopyo Jeong, Purdue University

Abstract

With the scaling of process technology and increase in integration density, the demand for high performance and low power consumption has become important in VLSI circuit design. In this thesis we propose methodologies to achieve low power consumption with high performance. In the first part of this thesis, we propose Dual Transition Preferentially Sized (DTPS) logic, which consists of dual datapaths using Preferentially Sized (PS) circuits. DTPS logic has good noise immunity and low power dissipation while achieving high performance. Hence, it is suitable for multistage buffers and critical sections of datapaths requiring high performance and low power consumption. High performance adders with low power consumption are essential for the design of high performance processing units. We also present a low power and high performance Carry Select Adder using DTPS logic. Demands for the low power VLSI circuits have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. In the second part of this thesis, we propose 3 different adaptive supply voltage scaling techniques. (1) We propose low power Ripple-Carry Adder (RCA) and Carry-Select Adder (CSA) using an adaptive supply voltage scaling technique. The proposed adders adaptively select supply voltages based on the input vector patterns. The proposed adder cancels out any delay penalty, utilizing two innovative techniques: a carry-skip technique on the checking operands, and the use of Complementary Pass Transistor Logic (CPL) with dual supply voltage for level conversion. (2) For recent technologies, the power consumption due to global buses and increased delay spread due to different load capacitances of buses have become important. Hence, we propose an adaptive supply voltage design technique for interconnects having different load capacitances. (3) Finally, we also propose an adaptive clustered Voltages Scaling (CVS) technique for pipelined systems, which monitors the transition of the worst delay of the slow pipeline stages, and adaptively adjust the lower supply voltage for the slow pipeline stages to reduce power consumption.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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