Analysis, design and optimization of on -chip global interconnections and communications

Ruibing Lu, Purdue University

Abstract

Integrated circuit design suffers from the design iteration problem due to the difficulty in accurately estimating the delay of global interconnects. To overcome the design iteration problem, we first study interconnect planning for pipelined interconnects. A new method is proposed to perform simultaneously interconnect planning and interconnect pipelining through retiming so as to minimize the design iterations between architectural design and interconnect planning. Repeater planning, an important step of interconnect planning, is also extended to consider insertion of both flip-flops and repeaters for pipelined global interconnects. We also study latency insensitive systems, which employ communication architecture that can tolerate arbitrary communication latencies. We formally model and analyze the performance of latency insensitive systems using max-plus algebra. We also propose an implementation of communication channels of latency insensitive systems that with proper queue sizing of the channels, guarantees optimal throughput performance. While latency insensitive protocol is for point-to-point communications, the shared media bus architecture is another commonly used on-chip communication method due to its simple topology and predictable delay. We propose two on-chip bus communication architectures that deliver better throughput performance by allowing multiple transactions in one bus cycle.

Degree

Ph.D.

Advisors

Koh, Purdue University.

Subject Area

Electrical engineering

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