Low power design techniques at architectural level

Hai Li, Purdue University

Abstract

With technology scaling and with high performance requirements, energy-efficient processor design is becoming more and more important. This work focuses on low-power design techniques for modern high-performance pipelined microprocessor at the architectural level. Data-retention gated-ground cache technique (DRG-cache) utilizes the concept of Gated-Ground to reduce leakage energy without significantly affecting performance by turning off the unused sections of cache. Deterministic clock gating (DCG) is an architectural level clock gating technique. It reduces dynamic power consumption by decreasing switching activities of circuit blocks. Supply-voltage scaling is an efficient way to reduce both dynamic and leakage power consumption by lowering the operating voltage and the clock frequency of processor simultaneously. Our work proposes two supply-voltage scaling techniques for high-performance microprocessors: L2-miss-driven variable-supply-voltage scaling (VSV) and error-tolerant self-adaptive variable supply-voltage (SAYS). VSV achieves power reduction without inordinate performance degradation by scaling down the supply-voltage of processor when its workload is low on L2-cache misses. SAVS is used for the fault-tolerant processor, which can work at a lower supply-voltage with errors. As the error rate of program changes, the processor can dynamically tune the supply-voltage in order to achieve the more power savings with a tolerable performance overhead. Our results show that these techniques are effective in power reduction. As high-performance microprocessor pipelines get deeper and leakage power becomes a more crucial factor with technology scaling, the effectiveness of our work will continue to be important.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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