Design of high performance, low power VLSI circuits for scaled technologies
Abstract
Scaling of CMOS technology has enabled a phenomenal growth in computing capability throughout the last 4 decades. With the number of transistors on a chip rapidly approaching 1 billion and the integrated cache memory dominating the chip area, leakage power management has become indispensable in high-end microprocessors for cost effective packaging and cooling solutions. Leakage power is also a concern in low-end mobile system-on-chips where the low standby power feature is crucial. This thesis explores joint circuit-device-architecture techniques to reduce or utilize the ever-increasing leakage current for high performance, low power VLSI processors. We first present a circuit style that exploits sub-threshold leakage to achieve ultra-low power consumption in applications where performance is of secondary concern. By simply lowering the supply voltage below the Vth (threshold voltage), static CMOS circuits can operate while consuming orders of magnitude less power than in strong inversion region. We show design of an adaptive filter using both circuit and architectural level optimization for sub-threshold operation. Next, we present leakage control techniques that can reduce the active leakage power in logic and memory using circuit, device, and architectural level optimization. We also propose leakage tolerant circuit styles targeted for sub-90nm technology generations. A process-compensated dynamic (PCD) circuit scheme, showing good promise for squeezing the robustness and delay distribution is described. On-die leakage sensors that can measure the process variation are introduced for low-cost, high-resolution on-chip leakage measurements. Finally, we present a process-variation-aware active leakage reduction scheme for on-die SRAM caches. A 0.18μm, 16K-Byte SRAM testchip shows that SRAM cell leakage is reduced by 94.2% (1.8V, room temperature) at a performance penalty less than 2%. Measurement results also indicate that the sleep transistor originally designed for reducing leakage offers 25% improvement in SRAM read stability.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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