Logic and physical synthesis of high performance circuits

Aiqun Cao, Purdue University

Abstract

With scaling of CMOS technology, design challenges such as high power dissipation, low noise immunity, and process variations become critical issues for high performance circuits. In this work, we address these issues in the synthesis of different high performance circuits, namely Domino logic circuits, skewed logic circuits, and regular pass transistor logic circuits. Domino logic is the most popular high performance dynamic. Synthesis of Domino logic typically requires costly logic duplication, which translates into high power and area penalties. We propose a synthesis scheme to reduce the duplication cost under certain timing constraints. In order to guarantee the robustness of such Domino circuits, we perform the logic optimization as a post-layout step. Skewed logic is a noise-tolerant static logic style that can achieve performance comparable to Domino. We propose a two-step synthesis scheme for skewed logic circuits. In the first step, an integer linear programming-based approach is used to overcome the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. In the second step, a dynamic programming-based heuristic is applied to achieve an optimal selective clocking scheme. Regular circuit structures can offset process variations and scale better with technology. A novel compact BDD structure, called Non-crossing ordered BDD (NCOBDD), which can be mapped directly to a regular pass transistor logic circuit, is proposed. A functional decomposition algorithm is also proposed to reduce the area and latency penalties of the circuits by mapping decomposed NCOBDDs instead of monolithic ones.

Degree

Ph.D.

Advisors

Koh, Purdue University.

Subject Area

Electrical engineering

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