Analysis and design of high speed interconnects

Guoan Zhong, Purdue University

Abstract

As the semiconductor technology continues to scale down, the parasitic effects of interconnects have begun to manifest themselves in interconnect delay and signal integrity due to the ever increasing die size and clock frequency. Consequently, interconnects have become the primary limit on system performance. In this thesis, we concentrate on the modeling, analysis, and design of high speed VLSI interconnects, with an emphasis on the on-chip inductive effects. We derive a new exact closed form formula for the extraction of on-chip mutual inductances. The new formula is numerically more stable than other exact formulas in the literature, and it forms the backbone of a new inductance extraction tool. We propose a new efficient and accurate on-chip inductance model, which uses the original inductance to exploit the sparsity of the reluctance matrix (inverse of the inductance matrix). We also propose an efficient and systematic method to determine the sparsity pattern using a reluctance-based metric. We propose a new metric for quantifying the long-range effect of inductive coupling. It considers both the shielding effect of inductance and the damping effect of resistance. It is used to analyze the effectiveness of shields on reducing inductive coupling. We propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In the twisted bundle layout structure, a group of signal nets intertwine with a ground line such that the magnetic fluxes arising from a signal net within the twisted group cancel each other.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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