Design considerations for high-performance low -power circuits for scaled technologies

Naran Sirisantana, Purdue University

Abstract

As we move further into deep submicron era, a new set of design issues challenge circuit designers in designing high performance low power systems. Three significant problems that occur with the continued scaling of devices are excessive leakage current, reduced noise immunity, and unreliability due to process variations. This work proposes novel logic styles and power optimization techniques for designing reliable high-performance low-power circuits aimed for future process technologies. For leakage tolerant design, multiple oxide thickness circuits (MoxCMOS) can be used to reduce static, dynamic, and gate tunneling leakage power with minimal impact on area and performance. For noise-tolerant high-performance designs, this research proposes Selectively Clocked Skewed Logic (SCSL), a new circuit style based on skewed logic. Such circuits can be used instead of dynamic circuits, such as Domino logic, to achieve high performance with better noise immunity. SCSL not only has better scalability than Domino logic, but also has lower power consumption due to selective clocking. Advanced techniques, such as time borrowing, multiple threshold voltages, multiple oxide thicknesses, and multiple supply voltages, can be applied to improve the performance and power consumption of SCSL circuits even further. For yield enhanced designs, the use of skewed logic also helps soften the manufacturing yield problem due to unreliability of components for scaled technologies. Yield enhancing techniques introducing controlled redundancy for manufacturing yield improvement are proposed in this thesis as well.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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