Novel methodologies to improve signal integrity of precharge -evaluate circuits in deep sub-micron regime

Yonghee Im, Purdue University

Abstract

The signal integrity issue has become more important with down-scaling of feature sizes, because cross-talk induced by capacitive as well as inductive coupling keeps increasing in the deep sub-micron (DSM) era. In particular, the signal integrity issue is more crucial in dynamic logic designs since dynamic logic sacrifices noise immunity to achieve high performance. We present new circuit design methodologies to improve the signal integrity of precharge-evaluate logic in the DSM era. The methodologies are targetted towards delay and functional failures due to cross-talk. To avoid delay faults, a novel circuit design methodology, named Optimized Over-laying Array-Based Architecture (O2ABA), is proposed to perform circuit design and Placement & Routing (P&R) simultaneously. It is concluded that interwire capacitance, denoted by Cinterwire, is minimal when two wires are placed at right angle (orthogonally) in different layers with the currents in the wires flowing in the same direction (in-phase signals). This observation can be implemented by grouping wires according to current direction and then aligning them in an orthogonal way along the edges of a rectangle-shaped imaginary cell, named unit cell. By minimizing Cinterwire due to out-of-phase signals (in which currents flow in the opposite direction), O2ABA not only reduces the possibility of delay faults, but also predicts the performance of a circuit even before layout, thereby guaranteeing timing closure and shortening time-to-market . In the second part, two separate methods are presented to reduce the possibility of functional failures: Clock As Shielding (CASh) and Logic-Aware Layout Methodology (LALM). Power-Ground network (P/G network) has been widely used to shield signal wires for better noise immunity. On the other hand, LALM utilizes circuit functionality to avoid functional faults by reordering transistors and/or nets. Transistor and/or net reordering have been used to improve delay and/or power, but it is for the first time we utilize the concept of reordering for better noise immunity. Unlike other noise tolerant circuits, neither CASh nor LALM degradates circuit speed. Moreover, both techniques can be integrated to improve noise immunity further.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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