High voltage silicon carbide UMOSFETS

Imran Ali Khan, Purdue University

Abstract

Silicon carbide has been the focus of intense research in recent years. Its higher breakdown field and higher thermal conductivity than silicon gives it the potential for high power applications with superior performance. To exploit these advantages, a vertical MOS-based power device is developed. The vertical orientation of the device takes advantage of the higher bulk electron mobility in that direction. This device structure has been optimally designed to potentially block 7.5kV in the off-state, while maintaining a high drive current in the on-state. To accomplish both design constraints, two technological innovations were implemented. First, the device design was improved through the incorporation of an extended p-bottom region. This design feature protects the gate oxide from high fields without significant loss of the drive current. Finally, the processing technique was improved with the invention of a self aligned implant mask to avoid degradation of the on-state from the p-bottom implant. The fabricated devices exhibit blocking voltages of 5.0kV with specific on-resistance of 105mΩcm2. These devices currently demonstrate the highest blocking voltage for a UMOSFET structure in SiC. The drive current of these devices exceeds those reported in literature having similar blocking voltages but different design structures. The advancement of MOS-based power devices in SiC are profoundly repressed by the low inversion channel mobility. Ongoing studies on SiC MOS structures have shown improvement of the inversion channel mobility on lateral devices, but there is no corresponding data for vertical devices. Part of this thesis, describes experiments performed in an attempt to bridge the information gap between lateral and vertical SiC MOS structures. The results of the experiments indicate that similar improvements are attainable on the sidewall of a vertical MOSFET (UMOS). Currently in the silicon community, the device dimensions are being scaled down aggressively, resulting in very thin thermal gate oxides. The resulting excessive gate leakage current has propelled the investigation of alternative insulators with high dielectric constants (k) as a replacement of thermal oxide. The final aspect of this thesis presents some of the exploratory work done on evaluating these high-k dielectrics as a supplant to thermal oxide for the gate insulator in SiC MOS power devices. The higher k-value can induce greater inversion channel charge for similar insulator electric fields, and so diminish the impact of low inversion channel mobility. Successful capacitors were formed with higher k values (about 10) but their high gate leakage did not provide a significant advantage over thermal oxides.

Degree

Ph.D.

Advisors

Cooper, Purdue University.

Subject Area

Electrical engineering

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