Power supply noise analysis for deep sub-micron (DSM) VLSI circuits
Abstract
As VLSI technology advances to gigascale integration, billions of transistors will be packed on a single chip working at gigahertz switching speed. As a result, a large number of simultaneous switching events in the circuitry can cause considerable noise over the power supply network. Power supply noise can cause severe performance degradation or introduce logic failures, and must be considered at each phase of the design process. In this research, we estimate the power supply noise, investigate its impact on circuit design and performance, and propose synthesis of power and ground networks for robust design. Both the resistive noise (IR drop) and the inductive noise (Ldi/dt) are addressed. The parasitic resistance (R), inductance (L) and capacitance (C) in the power supply network are explicitly formulated in the noise modeling. The power supply grids are modeled as a linear time invariant (LTI) RLC network. The switching events in the circuitry are approximated as time-varying current sources. An event-driven simulation based approach is used to extract the spatio-temporal correlations between the switching events for different input vectors. A time domain based approach and a frequency domain based approach are proposed for the analysis of the power supply noise. Experimental results on benchmark circuits show that the power supply noise can be as high as 35% Vdd. Decoupling capacitance allocation, which is crucial for power supply noise suppression, has been investigated as a post-floorplanning optimization problem. A noise-aware floorplanning methodology, which takes power supply noise into consideration during the floorplanning process, has been proposed.
Degree
Ph.D.
Advisors
Koh, Purdue University.
Subject Area
Electrical engineering
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