Development of a process flow for self -aligned double -gate MOSFET by tunnel epitaxy using nitrided thermal oxide as gate insulators
Abstract
A new process flow to realize the ideal self-aligned double-gate (DG) MOSFET was designed. The ideal DG MOSFET should have uniform and thin Si channel, low source-drain resistance and perfectly aligned top and bottom gates. In the new process flow, thin silicon channel was achieved by confined lateral selective epitaxial growth (CLSEG) or tunnel epitaxy. Elevated source/drain fan-out structure was used to reduce the series resistance. The top and bottom gates were self-aligned to each other and source/drain regions in the proposed structure. A novel single-crystal silicon gate structure was incorporated to reduce the poly depletion effects. Two key issues related to the proposed DG-MOSFET were identified. First, in the proposed structure, as the gate dielectrics are grown first and channel region is formed later by the epitaxial growth of silicon, the gate oxides can be significantly degraded due to the exposure to the selective epitaxial growth (SEG) ambient. A comprehensive study was carried out to quantify this degradation to gate dielectrics. Thickness of the gate dielectrics used in this study was ∼6 nm. Nitridation of thermal oxide was shown to significantly reduce the SEG ambient related degradation. Thermal oxides showed breakdown fields of less than 1 MV/cm and large leakage currents after exposure to the SEG ambient. On the other hand, nitrided oxide (NOX) showed only slight degradation in breakdown fields after SEG stress. Improvement in interface state density was observed after exposure to the SEG ambient from 4e10 to ∼1.5e10 cm −2 eV−1 for NOX samples. Also, the leakage current was significantly lowered after nitridation. The second key issue was the quality of the epitaxially grown silicon in the channel. A simplified single-gate MOSFET structure was designed to electrically characterize the material quality of the channel created by the tunnel epitaxy. Fabricated single-gate device showed good subthreshold slope of ∼70 mV/decade and low leakage current. Channel thickness as thin as ∼20 nm was achieved by tunnel epitaxy.
Degree
Ph.D.
Advisors
Neudeck, Purdue University.
Subject Area
Electrical engineering
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