Device Circuit Co-Design Utilizing Piezoelectric and Ferroelectric Materials

Niharika Thakuria, Purdue University

Abstract

The needs of the semiconductor industry in this era are heavily data-driven. While the processing demands have grown many folds due to the proliferation of data, the slow-down of dimension scaling has widened the gap between the computation needs and the technological capabilities of standard Complementary Metal Oxide Semiconductor (CMOS). Another key requirement for efficient data processing is large and fast memory systems, e.g., Complementary Metal Oxide Semiconductor (CMOS) based Static Random Access Memory (SRAM). However, dominance of leakage power has become a major concern for them at scaled nodes. These limitations of CMOS have guided towards finding solutions in emerging technologiesfor memory and information processing. On one hand, emerging steep switching devices promise enhanced drain current and/or lower leakage, alleviating the performance roadblock caused by slow-down of feature size miniaturization, without elevating leakage. On the other hand, emerging nonvolatile memories can augment or replace CMOS based memory technologies due to their desirable features like high density, low leakage, non-volatility, etc. Amongst different solutions, ferroelectric and piezoelectric materials possess interesting properties which, if harnessed properly, can address the needs for both logic and memory devices. Hence, piezoelectric (PE) and ferroelectric (FE) properties are being studied in conjunction with silicon and other channel materials to design new field effect transistors (FETs) as prospective emerging technologies towards an extended CMOS epoch. In this thesis, we aim to further the study of PE and FE coupled FETs in providing solutions towards (i) limitations of scaling (ii) alleviating the challenges in non-volatile memory design and (iii) enabling efficient computation-in-memory and other computational paradigms based on coupled oscillatory networks. To that effect, we study the piezoelectric strain based steep switching device - 2D-SFET. The unique device structure and steep switching mechanism of 2D-SFET couples piezoelectric induced strain (in PMN-PT) with bandgap modulation of 2D Transition Metal Dichalcogenide (2D-TMD such as MoS2) in the channel, and offers several opportunities for device-circuit co-design and application in circuits. We propose technology-aware circuits viz. Schmitt trigger (ST) with two 2D-SFET (2T ST) and 2D-SFET based SRAMs and study the interactions between device and circuit optimization parameters with an aim establish the benefits and drawbacks of application of 2D-SFETs in circuits. Our design of 2T ST based on back voltage (VB)-aided bandgap modulation of 2D-SFETs shows 5× lower energy and 22% lower rise/fall time at iso-hysteresis compared to standard ST based on six transistor (2D FET) design. With regards to 2D-SFET 6T SRAM, we propose various flavors by leveraging VB driven dynamic bandgap change in 2D-SFET. Our designs are aimed at increasing stability, thereby mitigating design conflicts of 6T SRAM with 2D-SFET as a drop-in replacement. Our analysis shows maximum benefits in 2D-SFET Dual Wordline (ST-DWL) SRAM, of up to 35%, 115% and 11% improvement in read stability, write margin and hold margin with comparable access time and write time with 2D-FET 6T SRAM, albeit with architectural changes. All the proposed 2D-SFET VB-enabled SRAM designs achieve the enhanced functionalities at iso-area and 22% overhead compared to 2D-SFET (drop-in) and 2D-FET 6T SRAM respectively. The next study is related to ferroelectricity/piezoelectricity driven non-volatile memory (NVM) designs. We propose Piezoelectric Strain FET (PeFET) that utilizes a piezoelectric/ferroelectric (PE/FE such as PZT) coupled with a FET designed with 2D-TMD channel (such as monolayer MoS2).

Degree

Ph.D.

Advisors

Gupta, Purdue University.

Subject Area

Energy|Artificial intelligence|Computer science|Design|Electrical engineering|Electromagnetics|Physics

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