Ultra -low power digital sub-threshold logic design

Hendrawan Soeleman, Purdue University

Abstract

The increasing demand for portable and mobile applications has resulted in significant growth in low-power design. Many existing circuit techniques have been successfully applied in the medium power, medium performance region of the design spectrum. However, in many applications, where ultra-low power consumption is the primary requirement and performance is of secondary importance, more aggressive techniques are warranted. To satisfy this ultra-low power requirement, we introduce a new set of logic family: digital sub-threshold logic. In sub-thresbold logic, all transistors operate in the weak inversion region instead of the normal strong inversion region. The minute sub-threshold current of the transistor is used as the switching current to obtain the ultra-low power consumption. Using a regular 8 x 8 carry-save array multiplier as a test vehicle, simulation results show that a savings in energy/switching of 2 orders of magnitude can be obtained by sub-threshold logic with power supply, VDD = 0.5V, over normal strong inversion logic with VDD = 3.3V in TSMC 0.35μm technology. Sub-threshold logic also consumes less energy/switching than other known low-power logic, such as energy-recovery logic. Due to the completely different characteristics of the transistor in the weak inversion region, subthreshold logic correspondingly has different characteristics than its strong inversion counterpart, in terms of trans-conductance, gain, noise margin, power, delay, sensitivity to process and temperature variations, etc. Various logic styles, such as: static, ratio-ed and dynamic sub-threshold logic are described, compared and analyzed in this dissertation. To validate the operation of sub-threshold logic, a testchip has been fabricated using TSMC 0.35μm technology through MOSIS. The threshold voltages of PMOS and NMOS are 0.82V and 0.67V, respectively. Our experiment results on the testchip shows that the logic still operating properly in the deep sub-threshold region with Vdd = 0.3V i.e. much lower than the threshold voltage of the transistor.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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