Testing solutions for intrinsically leaky CMOS integrated circuits
Abstract
This thesis examines the impact of technology scaling, in the deep submicron regime, on the testability of high performance CMOS integrated circuits (ICs). A significant barrier to technology scaling is transistor leakage current. Excessive increase in transistor leakage current, and its variability due to parameter variation, challenge design, testing, and reliability of ICs. As a result, the effectiveness of well-established IDDQ-based test techniques may diminish. Our research objective is to enable leakage-based testing, in particular IDDQ-sensitive measurements for intrinsically leaky integrated circuits. This dissertation focuses on testing and design of low voltage and high performance CMOS ICs. We have characterized the components of transistor and circuit leakage by measuring their sensitivities across channel length, threshold voltage, temperature, body bias, and frequency. These transistor and circuit measurements resulted in the development of a new testing solution for ICs with high and variable background leakage current. This correlative, intrinsic, device physics based test method is called multiple-parameter testing. The two-parameter IDDQ combined with frequency (F MAX) is our primary test solution. This improves yield by rescuing very fast ICs from fall out to traditional IDDQ test while screening defective ICs. The speed-dependent leakage limit in this test enhances its sensitivity. Additionally, IDDQ versus FMAX test inherently accounts for parameter variation. We have further improved the signal to noise ratio of the two-parameter test technique by applying a third variable such as reverse body bias (RBB) or temperature. In a 0.18 μm technology, temperature was most effective and improved the sensitivity of IDDQ versus FMAX two-parameter test by more than an order of magnitude (13.8X from 110°C to 27.7°C). Finally, we have developed and experimentally verified an optimum reverse body bias for maximum static (standby) leakage power reduction in deep submicron ICs.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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