Low power BIST

Xiaodong Zhang, Purdue University

Abstract

Power minimization and test length reduction are two objectives for BIST (Built-In-Self-Test). To reduce average power and test length for combinational circuits, we propose a low power random testing technique, in which signal probabilities (probability of signals being logic ONE) are optimized for minimum test length, and signal activities (probability of signal switching) are optimized for minimum average power. The corresponding programmable low power ATP generator has been implemented using cellular automata or LFSR with external weighting logic. An average power reduction of 80% is achieved for ISCAS benchmark circuits. In sequential circuits with scan design, most of signal activities occur in the scan chain. We propose a scan chain re-ordering technique which reduces the number of signal switchings in the scan chain up to 43%. For very large systems, a careful scheduling of test is necessary to avoid maximum power rating violation. We propose a fault coverage macro-model and an average power macro-model which is used in efficient test scheduling. The fault coverage is maximized by searching the optimum signal probabilities, the average power is minimized by searching the correct signal activities, and the test length is minimized by carefully scheduling the circuit blocks for test. Besides the average power consumption, peak power dissipation is also important. In order to reduce peak power during test, we propose three techniques: the first one is to search the optimal initial states in CA cells; the second one is to restrict the number of active primary inputs, and the third one is to eliminate the high power vectors.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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