Multiple layers of silicon on insulator islands fabrication process by selective epitaxial growth for three-dimensional ULSI
Abstract
Multiple layers of Silicon-on-Insulator (MLSOI) device islands fabrication process was developed for the first time utilizing selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration and provides alternative three-dimensional approach of fabricating devices in a stacked manner. SOI device island size as small as 150nm x 150nm up to 8μm x 600μm, and SOI thickness down to 40nm have been fabricated. The SOI island fabrication consists of pre-defining recessed wells in the field oxide in which ELO is grown and excess SEG is polished away by chemical mechanical planarization (CMP). This method allows creating very thin and smooth SOI islands surrounded by oxide. Repeating the process on the low temperature PECVD deposited second field oxide allows the formation of second layer SOI islands. Any of the exposed silicon from the first layer, i.e., SOI island, ELO, or SEG seed, can be used as atomic template to grow second or higher level SOI. Two methods were used to verify the device material quality of the MLSOI islands. First, stacking fault studies indicated the almost defect-free in both layers of SOI islands. Second, deep-submicron fully-depleted SOI P-MOSFETs were made in two different stacked SOI layers. Several key process steps, such as growing thin gate oxide (60Å), modified E-beam lithography to define gate length down to 0.1 μm, and self-aligned Platinum silicide (PtSi) to lower series resistance, were developed. Although the DC characteristics were limited by large series resistance due to large contact spacing (by optical alignment limitation), the measured 0.2μm fully-depleted SOI P-MOSFET devices had excellent electrical performance; drive current over 240μA/μm, off-state leakage currents below 0.2pA/μm, and subthreshold swing of 66.6mV/dec. The devices in the second SOI layer showed similar electrical characteristics.
Degree
Ph.D.
Advisors
Neudeck, Purdue University.
Subject Area
Electrical engineering
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