Spur reduction techniques for fractional-N frequency synthesizers

Fazil Ahmad, Purdue University

Abstract

Frequency synthesizer is an essential circuit block for up conversion and down conversion in transmitters and receivers respectively. Fractional-N frequency synthesizers are replacing conventional integer- N frequency synthesizers because of their better performance in terms of settling time and phase noise. However, fractional-N frequency synthesizers suffer from fractional spurs or side bands which increase errorvector magnitude (EVM). To solve the fractional spur problem various techniques are suggested in the literature but have limitations in terms of area and power. To reduce the limitations, two fractional-N phase-locked loop (PLL) architectures are proposed where the phase is locked in each reference cycle unlike conventional sigma delta PLLs. This reduces fractional spurs and increases bandwidth. The proposed architectures are compared with sigma delta, finite impulse response (FIR) filtering based sigma delta and multi-phase voltage controlled oscillator (VCO) based fractional-N PLLs. The proposed architectures and its algorithm to generate many divide-by-N outputs by one divider is proved mathematically and behavioral simulations and full transistor level simulations are done to verify it. Simulations show removal of sigma delta quantization noise which improves both broadband phase noise and fractional spurs. Implementation challenges like deterministic mismatch and random mismatch are also considered and sigma delta modulator and butterfly scrambler are used to compensate mismatch. This reduces the worst case fractional spur by 10dBc and 28dBc respectively in the proposed architecture with multiple phase frequency detectors (PFDs). Various cases of digital sigma delta are discussed in trade off perspective.

Degree

M.S.E.C.E.

Advisors

Jung, Purdue University.

Subject Area

Electrical engineering

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