Finfet device optimization at 15nm for near-threshold operation
Abstract
Much of the current research in the electronic industry focuses on reducing power consumption of digital circuits. Towards the same many attempts are being made to reduce the operating voltage of the circuits. It has been shown through device and circuit analysis that a circuit consumes minimum energy when operated near threshold voltage. In this thesis I vary device parameters and study their effects on energy consumption and delay of the device for the two regions of operation - superthreshold and near-threshold, using LUTs of IV and CV characteristics, verilogA and hSpice. Finally, device parameters are obtained for an optimum superthreshold optimized device which acts as the baseline device, and for a near-threshold optimized device. The savings in energy are calculated when near-threshold optimized devices are used instead of baseline devices for circuits that are being operated near threshold voltage.
Degree
M.S.E.C.E.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our
proxy server.