Pad assignment for system-in-package design

Namita Negi, Purdue University

Abstract

Similar to SoC (System-on-Chip) design, System-in-Package (SiP) design encloses a number of integrated circuits in a single package. In an SiP design the system is implemented as a number of integrated circuits, each of which is placed on a different die. A system is partitioned into dies in such a way that the number of inter-die connections is minimized. These dies can be stacked vertically on a substrate. An inter-die signal between two dies is realized by connecting any two pads on the dies using a bond-wire; these pads are located mainly on the peripheral of the dies. The number of signals which can be assigned by direct inter-die connections is decided by the wire bonding resolution. When two dies cannot be connected directly, the substrate is used to complete the routing. This affects the performance and the cost of SiP design. Therefore it becomes necessary to maximize the number of signals between two dies that can be connected directly. Pad assignment is an important stage in SiP design which is used to accomplish this objective by assigning signals to the pads. Given the number of inter-die signals, this work aims at obtaining a pad assignment solution, while minimizing the wire length. First, sub-problems are identified which can be solved optimally without affecting the quality of the overall solution. Second, an Integer Linear Programming (ILP) formulation is used to solve the remaining problem. Finally, the solution obtained is further improved by a post processing technique. Experimental results showed that the heuristic is effective in reducing the wire length in a reasonable amount of time. The heuristic has been tested on several test cases with different number of dies, inter-die signals and pads, where the pads are uniformly distributed on all the four sides.

Degree

M.S.E.C.E.

Advisors

Raghunathan, Purdue University.

Subject Area

Electrical engineering

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