Self-repairing static random access memory (SRAM) using on-chip detection and compensation technique

Niladri Narayan Mojumder, Purdue University

Abstract

In nano-meter scale SRAM arrays, systematic inter-die and random within-die variations in process parameters can cause significant parametric failures. In this dissertation, we investigate the joint impact of the inter-die and intra-die threshold voltage variations on SRAM read and write failures. To improve the robustness of an SRAM cell, we propose a closed-loop compensation technique using on-chip monitors that directly sense the global read stability and writability of the cell. Simulations based on 45 nanometer Partially Depleted Silicon On Insulator (PD/SOI) technology demonstrate the viability and the effectiveness of the proposed scheme in SRAM yield enhancement.

Degree

M.S.E.C.E.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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