Optimum Control of Inverter Voltage Edge Rate in Variable-Speed Motor Drive Systems
Abstract
Power-electronic-based dc-to-ac inverters are used in numerous applications such as hybrid and electric vehicles, aircraft actuators, ship propulsion, and grid integration of renewable energy sources, to name a few. Depending on the voltage and current levels, the inverters are typically composed of metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). To increase switching frequencies while limiting corresponding switching losses, these transistors have been made significantly faster with achievable switching times now less than 100 ns. However, as power transistors have become faster, the inverter output voltage edge rate ( dv/dt) has become correspondingly larger. In variable-speed drive systems, various deleterious effects attributed to high dv/dt have been observed, including transient over-voltages at the motor terminals, electromagnetic interference, and bearing failures due to micro arcs. A common approach for limiting dv/dt involves the insertion of a passive filter between the inverter and motor or generator. However, the dv/dt filter introduces new losses and increases the overall size and weight of the inverter. Soft-switching circuits, such as the auxiliary-resonant-commutated-pole inverter, can reduce dv/dt and switching losses but have other drawbacks. In this thesis, a new soft-switched circuit, entitled the auxiliary resonant soft-edge pole (ARSEP), is set forth. Different control methods are described together with parameter-design procedures. A prototype ARSEP circuit was designed, simulated, and constructed to verify its performance and benefits. Compared with a conventional inverter with dv/dt filter, the ARSEP prototype results in a 24% reduction in overall losses, 45% reduction in inductor volume and 61% reduction in inductor weight.
Degree
Ph.D.
Advisors
Wasynczuk, Purdue University.
Subject Area
Engineering|Electrical engineering
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