Towards Integration of Graphene in Advanced CMOS Interconnect Technology

Ruchit Mehta, Purdue University

Abstract

The integration of graphene into existing state-of-the-art semiconductor manufacturing is a topic of worldwide interest. With its unprecedented electrical, thermal and mechanical properties, graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to demonstrate BEOL-compatible graphene growth techniques, and explore various avenues for practical integration of graphene in order to achieve better electrical, thermal and reliability metrics than traditional interconnect technology. Specifically, we focus on developing robust low-temperature graphene growth techniques with high yield to meet the stringent thermal budgets of BEOL processing. We demonstrate high yield graphene growth on Cu thin films, Cu nanowires and dielectrics at 550 °C by optimizing a plasma-enhanced chemical vapor deposition (PECVD) process. This permitted the first experimental evaluation of the enhanced electrical and thermal properties of Cu-G hybrid nanowires. Encapsulation of Cu nanowires with graphene increases the Cu electrical conductivity by 15% and thermal conductivity by 25% compared to uncoated nanowires. Deposition of graphene on Cu nanowires reduces the surface Cu oxide and allows corrosion stability over long periods. Interestingly, graphene being a low density-of-states material introduces partially specular scattering of electrons at the surfaces of Cu-G nanowires. As dimensions scale down further, the benefits of higher conductivity, lower Joule heating and higher breakdown current density from Cu-G interconnects are expected to be even more prominent. In addition, we explicitly measure in-plane thermal conductivity enhancement in Cu-G films using a suspended heater-sensor platform. Concurrently, we estimate thermal boundary resistance for heat flow across the Cu/graphene/dielectric interface using time-domain thermoreflectance (TDTR) measurements. This study provides valuable insights for heat management applications using Cu-G hybrids. Furthermore, moving to a Cu-G interconnect technology necessitates low temperature graphene deposition not only on Cu but also directly inside dielectric trenches. In doing so, graphene must replace conventional Cu diffusion barriers. Using time-dependent bias-temperature stress experiments, we show that transfer-free multi-layer graphene (MLG) membranes on dielectrics are remarkably good at blocking Cu-ion transport. Compared to a Ta barrier of same thickness, MLG offers superior diffusion barrier performance coupled with the electrical and thermal benefits of an improved interface with Cu.

Degree

Ph.D.

Advisors

Chen, Purdue University.

Subject Area

Electrical engineering|Nanoscience

COinS