Integrated Transceiver Front-end for High-FrequencyWireless Communications
Abstract
A renaissance of wireless and wired communications in the last decade has engaged with advanced CMOS technology to achieve the contradictional goal of low cost and high performance. The demand for a low-cost, high performance wireless front-end system and aggressive device scaling has triggered intensive research on CMOS radio-frequency (RF) front-end circuits. Most of emerging standards have been implemented and will be implemented by CMOS technology. Besides the advanced CMOS technology, recent researches in wireless transceiver design have focused on full integration solution of a transceiver which contains digital and RF/analog circuits using low-cost CMOS technology. Interferences and interfaces between RF/analog and digital circuits need to be dealt with carefully to prevent degradation of signal integrity. The demands for high speed wired and wireless communications are ever increasing as a data rate is increased, and the radio-frequency integrated circuits (RFICs) satisfying all design specification requirements become even more challenging. The higher demands for portable communication devices supporting multiple standards encourage combining multiple systems on a single product, and the product cost is directly proportional to numbers of integrated wireless systems. Therefore, it is crucial to reduce or share the building blocks on the front-end while keeping system performance. In addition to the multi-standard approach, several new communication standards have suggested and announced in order to improve legacy standards or to comply new consumer market demands. This research focuses on four separate topics that are important for low cost and high performance wireless communications. Chapter 2 presents a new gm-boosted common-source LNA topology. The proposed LNA improves NF by increasing the effective transconductance of the input device in its input matching network. The detailed theoretical analysis and comparisons of NF for different topologies are discussed. In Chapter 3, a non-coherent receiver design is described for a 6-Gbps wireless inter-chip data link using bond-wire antennas. The system uses binary ASK modulation to keep the design compact and power efficient. In Chapter 4, we discuss an IR-UWB transceiver design supporting IEEE 802.15.4a standard, analysis on how to improve the ranging and communication performance, and how to save power consumption in the IR-UWB transceiver are included. The system and circuits details in 0.13 μm CMOS are presented. Chapter 5 describes UWB LNA and active balun. It includes how the proposed topology improves signal balance in detail through theoretical analysis and simulations, and provides a design guide for an optimal design.
Degree
Ph.D.
Advisors
Jung, Purdue University.
Subject Area
Electrical engineering
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