Scaling issues and solutions in ultra scaled MOSFETs using predictive modeling
Abstract
Channel length of metal oxide semiconductor field effect transistors (MOSFETs) are scaling below 20 nm. At this scale, quantum mechanical effects, including source to drain tunneling and quantum confinement play an increasingly important role in predicting device performance. Accurate projections of device characteristics are of high interest in the semiconductor industry. This work presents a semi-empirical model based quantum transport tool, which is used for accurately predicting the performance of double gate MOSFETs over the next 15 years as part of the International Technology Roadmap for Semiconductors (ITRS). The results show ON-current and performance degradation as a result of source to drain (SD) tunneling, and band structure alteration and supply voltage reduction due to scaling. Furthermore, the impacts of SD tunneling in ultra-scaled devices are investigated. In particular, heavy mass materials and the lightly doped drain are proposed as solutions for SD tunneling. Thick gate stacks can degrade electrostatics in ultra-scaled MOSFETs. Here, we present an approach to find optimum oxide thicknesses in order to prevent gate leakage and optimize device electrostatics. Lastly, we analyze the confined SiGe based P-type MOSFET as a promising candidate for the next technology node in the semiconductor industry. Reducing the thickness of the <110> SiGe channel improves ballistic ON-current and increases the band gap, which is favored for reducing leakage. These changes are quantified and shown to become more pronounced for higher germanium percentages. Moreover, while strain plays an important role in improving the ballistic ON current, this effect diminishes for very thin channel thicknesses.
Degree
Ph.D.
Advisors
Klimeck, Purdue University.
Subject Area
Computer Engineering|Electrical engineering|Condensed matter physics
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