Device-circuit analysis of sub-10nm double-gate FinFETs for energy efficiency
Abstract
Sub-10nm gate length transistors have severe short channel effects along with new leakage mechanisms such as direct source-to-drain tunneling (DSDT). Also, ultra-thin body of the device brings strong quantum confinement effect and increases source/drain series resistance (RS/D) leading to performance loss. In this dissertation, we explore the design space of sub-10nm gate length double-gate FinFETs (DGFETs), and optimize the devices to counter all these effect in deeply scaled technologies. This research also focuses on device-circuit co-simulation and analysis of energy efficiency in such a deeply scaled technology for logic and memory. To that effect, first, we investigate the effects of crystal orientation on transport characteristics of n- and p-type unstrained Si DGFETs in sub-10nm regime considering DSDT. For that purpose, we perform atomistic quantum simulation, and analyze the effects of quantum confinement on the effective masses using their bandstructure. We also explore the impact of variations in the body thickness on the ION and the IOFF of the devices with different sidewall and channel direction. We show that (100)/<100> n- and p-type unstrained Si DGFETs have advantages over (110)/<110> devices in sub-10nm regime with respect to ION/IOFF and the body thickness variation. Next, we perform comparative device-circuit analysis of DGFETs and double-gate Schottky Barrier FETs (SBFETs) using mixed-mode simulation in order to compare their suitability for sub-10nm technologies. We explore their design space and analyze the joint impact/trade-off of DSDT and RS/D on device parameters such as body thickness and gate-to-S/D underlap. The benefits and tradeoffs associated with these parameters are evaluated. Based on the device analysis, we also investigate logic and memory designs in terms of performance, energy, and stability. Our analysis show that DGFETs provide higher drive strength (even with larger source/drain series resistances) compared to SBFETs. As a result, DGFET-based logic show higher performance, and better read stability for memory while SBFET-based memory showed higher write stability. Finally, we show that by designing devices with asymmetric source and drain, read-write design conflicts in sub-10nm 6T SRAM can be mitigated and larger cell stability can be achieved. To that effect, we optimize the devices with asymmetric gate underlap on the source and the drain sides. We also propose devices, in which one side of source/drain is replaced by metal. Based on the features of those devices, we analyze their impact on the cell stability and performance of 6T SRAM bit-cell. We also discuss the effectiveness of supply-gating in sub-10nm technology. We report that supply-gating technique effectively works to improve standby leakage for this deeply-scaled technology by reducing DSDT current as well as thermionic leakage current.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
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