Date of Award

Spring 2015

Degree Type


Degree Name

Master of Science in Electrical and Computer Engineering (MSECE)


Electrical and Computer Engineering

First Advisor

Irith Pomeranz

Committee Chair

Irith Pomeranz

Committee Member 1

Anand Raghunathan

Committee Member 2

Vijay Raghunathan


All products in the Very-Large-Scale-Integrated-Circuit (VLSIC) industry go through three major stages of production - Design, Verification and Manufacturing. Unfortunately, neither of these stages are truly perfect, hence we need two more sub-stages of manufacturing, namely Testing and Defect Diagnosis to prevent imperfections in ICs. Testing is used to generate test vectors to validate the functionality of the Device-under-Test (DUT), and Defect Diagnosis is the process of identifying the root-cause of a failing chip, i.e., the location and nature of defect. Systematic defects are unintended structural and material changes at specific locations with a higher probability of failure due to repeating manufacturing imperfections. While Design-For-Manufacturability (DFM) guidelines are not always applied due to limited resources like circuit area and design time, enforcing these guidelines helps in ensuring sufficient product yields by preventing systematic defects. However, even if the DFM guidelines are strictly enforced, systematic defects may still occur as complete information about the process and manufacturing is not available due to reducing available time-to-market for chips. ^ An earlier work used DFM guidelines as a basis for modeling of defects, and diagnostic test generation. Under this framework, a circuit is processed to identify layout locations that violate DFM rules. Next, these coordinates are mapped and translated to faults based on different fault models including stuck-at-faults, bridging faults and transition faults. ^ The goal of this thesis is to perform systematic defect diagnosis and analyze the accuracy of diagnosis under the same DFM framework. Thus, systematic defect candidates are generated from DFM guidelines and the generated faultlist is used to perform diagnosis. Because defects may not always be systematic, a new heuristic to dynamically switch between DFM and non-DFM faultlists has also been implemented. This presents us with the best option to follow to further optimize the accuracy of diagnosis. The results demonstrate that the DFM framework can be used to improve the accuracy of diagnosis with minimal resource requirements.