III-V-on-nothing metal-oxide-semiconductor field-effect transistors enabled by top-down nanowire release process: Experiment and simulation

J. J. Gu, Purdue University
O. Koybasi, Purdue University
Y. Q. Wu, Purdue University
Peide D. Ye, Birck Nanotechnology Center, Purdue University

Date of this Version



Applied Physics Letters: Volume 99, Issue 11


Copyright (2011) American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics. The following article appeared in Applied Physics Letters: Volume 99, Issue 11 and may be found at http://dx.doi.org/10.1063/1.3638474. The following article has been submitted to/accepted by Applied Physics Letters. Copyright (2011) J. J. Gu, O. Koybasi, Y. Q. Wu, and P. D. Ye. This article is distributed under a Creative Commons Attribution 3.0 Unported License.


III-V-on-nothing (III-VON) metal-oxide-semiconductor field-effect transistors (MOSFETs) are experimentally demonstrated with In0.53Ga0.47As as channel and atomic layer deposited Al2O3 as gate dielectric. A hydrochloric acid based release process has been developed to create an air gap beneath the InGaAs channel layer, forming the nanowire channel with width down to 40 nm. III-VON MOSFETs with channel lengths down to 50 nm are fabricated and show promising improvement in drain-induced barrier lowering, due to suppressed short-channel effects. The top-down processing technique provides a viable pathway towards fully gate-all-around III-V MOSFETs. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3638474]


Nanoscience and Nanotechnology